The present invention relates generally to network interfacing, and more particularly, to a system for controlling transmission of data between network stations connected to a network medium and a device and method for setting a sampling clock rate to one of multiple clock rates based on the received signal format.
The transmission of various types of digital data between computers continues to grow in importance. The predominant method of transmitting such digital data includes coding the digital data into a low frequency base data signal and modulating the base data signal onto a high frequency carrier signal. The high frequency carrier signal is then transmitted across a network cable medium, via RF signal, modulated illumination, or other network medium, to a remote computing station.
At the remote computing station, the high frequency carrier signal must be received and demodulated to recover the original base data signal. In the absence of any distortion of the carrier signal across the network medium, the received carrier would be identical in phase, amplitude, and frequency to the transmitted carrier and could be demodulated using known mixing techniques to recover the base data signal. The base data signal could then be recovered into digital data using known sampling algorithms.
However, the network topology tends to distort the high frequency carrier signal due to numerous branch connections and different lengths of such branches causing numerous reflections of the transmitted carrier. The high frequency carrier is further distorted by spurious noise caused by electrical devices operating in close proximity to the cable medium. Such problems are even more apparent in a network which uses home telephone wiring cables as the network cable medium because the numerous branches and connections are typically designed for transmission of plain old telephone system POTS signals in the 0.3-3.4 kilohertz frequency range and are not designed for transmission of high frequency carrier signals on the order of 7 Megahertz. Further yet, the high frequency carrier signal is further distorted by turn-on transients due to on-hook and off-hook noise pulses of the POTS utilizing the network cables.
Such distortion of frequency, amplitude, and phase of the high frequency carrier signal degrades network performance and tends to impede the design of higher data rate networks and challenges designers to continually improve modulation techniques and data recovery techniques to improve data rates. For example, under the HPNA 1.0 standard, a 1 Mbit data rate is achieved using pulse position modulation (PPM) of a carrier, while the more recent 2.0 standard achieves a 10 Mbit data rate using a complex modulation scheme utilizing a frequency diverse quadrature amplitude modulation (QAM).
A problem associated with advancing standards and increasing data rates is that, as in the HPNA example, the modulation techniques are not the same. As such, backwards compatibility is not inherent in the design of the newer systems. For example, in the HPNA system, to be backwards compatible, the newer 2.0 receiver must be able to demodulate both the PPM modulated carrier compliant with the 1.0 standard and the frequency diverse QAM modulated carrier compliant with the 2.0 standard. As such, many of the functions in the receiver must be implemented in two distinct circuits, one circuit for the PPM and one circuit for the QAM, thereby increasing the cost and complexity of the receiver.
Receivers typically include an A/D converter for sampling the modulated carrier signal and generating a series of samples occurring at a sample frequency. The series of samples are input to the remainder of the receiver circuitry that is typically implemented on a digital signal processor (DSP).
The complexity of the mathematics performed by the DSP is a function of various parameters including the sample frequency. The complexity of the mathematics also affects gate count and thus the size and cost of the DSP. As such, for a particular carrier modulation specification, the A/D sample frequency can be selected to minimize DSP gate count to reduce the DSP size and cost.
The problem exists in that the optimal sample frequency for one carrier modulation specification may not equal the optimal sample frequency for a second carrier modulation specification thereby requiring two A/D converters. Therefore, based on recognized industry goals for size and cost reductions, what is needed is a device and method for obtaining a series of samples representing a modulated carrier at two different sample frequencies but not requiring two A/D converters.
A first aspect of the present invention is to provide a network receiver configured for receiving a modulated carrier signal representing a frame of data from another network transmitter via a network medium. The network receiver comprises an analog to digital converter generating a sequence of digital samples representing the modulated carrier signal. The sequence of digital samples occur at an A/D clock frequency. A frame detection circuit sets the A/D clock frequency to a first sampling frequency when a first frame specification is detected and sets the sampling clock frequency to a second sampling frequency when a the first frame specification is not detected.
The network receiver may further include a receiver circuit recovering data from the digital samples and generating a frame type signal indicating the frame specification. The first frame specification may utilize pulse position modulation of the carrier signal. A second frame specification may utilize quadrature amplitude modulation of the carrier signal and a third frame specification utilizes a combination of pulse position modulation of the carrier signal and quadrature amplitude modulation of the carrier signal.
The frame detection circuit may include a carrier sense circuit for detecting the duration of a power pulse in an envelope signal and the envelope signal may represent the square root of the sum of the square of the I channel carrier signal and the square of the Q channel carrier signal.
The frame detection circuit may set the A/D clock frequency to the first sampling frequency when the duration of a power pulse is less than a duration on the order of a duration of a pulse position modulation power pulse and the frame type signal does not indicate the third frame type. Further, the frame detection circuit may set the A/D clock frequency to the second sampling frequency when power pulses of a duration on the order of a pulse position modulation power pulse are not detected or when the frame type signal indicates one of the second and third frame type.
A second aspect of the present invention is to provide a method of determining an A/D clock setting for sampling a modulated carrier signal representing a data frame in a receiver configured for receiving a modulated carrier signal from a network medium. The method comprises: a) detecting whether the frame corresponds to a first modulation specification; b) selecting a first A/D clock setting in response to detecting a frame corresponding to the first modulation specification; and c) selecting a second A/D clock setting in response to not detecting a frame corresponding to the first modulation specification.
The method may further include detecting whether the frame corresponds to a second modulation specification and whether the frame corresponds to a third modulation specification. The first frame specification may utilize pulse position modulation of the carrier signal. A second frame specification may utilize quadrature amplitude modulation of the carrier signal and a third frame specification utilizes a combination of pulse position modulation of the carrier signal and quadrature amplitude modulation of the carrier signal.
The method may further include detecting the duration of a power pulse in the carrier signal. A/D clock frequency may be set to the first sampling frequency when the duration of a power pulse is less than a duration on the order of a duration of a pulse position modulation power pulse and third frame type is not detected. A/D clock frequency may be set to the second sampling frequency when power pulses are of a duration on the order of a pulse position modulation power pulse and the third frame type is not detected or when one of the second frame type and the third frame type are detected.